Con guration Sequencing with Self Con gurable Binary Multipliers

In this paper we present a hardware design technique which utilises runtime recon guration for a particular class of applications. For a multiplication circuit implemented within an FPGA, a speci c instance of multiplying by a constant provides a signi cant reduction of required logic when compared to the generic case when multiplying any two arbitrary values. The use of recon guration allows the speci c constant value to be updated, such that at any time instance the constant multiplication value will be xed, however over time this constant value can change via recon guration. Through investigation and manipulation of the sequence of required multiplication operations for given applications, sequences of multiplication operations can be obtained where one input changes at a rate slower than the other input. That is one input to the multiplier is xed for a set number of cycles, hence allowing it to be con gured in hardware as a constant and recon gured at the periodicity of its change. Applications such as the IDEA encryption algorithm and every cycle Adaptive FIR ltering are presented which utilise this recon guration technique providing reduced logic implementations while not compromising the performance of the design.